题解 | #数据累加输出#

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);
reg		[2:0]		count ;

assign ready_a = !valid_b | ready_b ;

always @(posedge clk or negedge rst_n ) begin
	if(!rst_n) begin
		count <=3'b0 ;
	end
	else if(ready_a && valid_a) begin
		count <= (count == 3'd3) ? 3'b0 :count + 3'b1 ;
	end
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_out <= 10'b0 ;
	end
	else if(count == 3'b0 && ready_b && valid_a && ready_a) begin
		data_out <= data_in ;
	end
	else if(ready_a && valid_a) begin
		data_out <= data_in + data_out ;
	end
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		valid_b <= 1'b0 ;
	end
	else if(count == 3'd3 && ready_a && valid_a) begin
		valid_b <= 1'b1 ;
	end
	else if(ready_b && valid_b) begin
		valid_b <= 1'b0 ;
	end
end
endmodule