题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
reg		[5:0]		data_6b ,count;
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		ready_a <= 1'b0 ;
	end
	else begin
		ready_a <= 1'b1 ;
	end
end
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_6b <= 6'b0 ;
	end
	else if(valid_a) begin
		data_6b <= {data_a , data_6b[5:1]} ;
	end
	else begin
		data_6b <= data_6b ;
	end
end
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_b <= 6'b0 ;
	end
	else if(count == 6'd5) begin
		data_b <= {data_a , data_6b[5:1]} ;
	end
	else begin
		data_b <= data_b ;
	end
end
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		count <= 6'b0 ;
	end
	else if(count == 6'd5) begin
		count <=6'b0  ;
	end
	else if(valid_a) begin
		count <=count + 1'b1  ;
	end
	else begin
		count <= count ;
	end
end
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		valid_b <= 1'b0 ;
	end
	else if(count == 6'd5) begin
		valid_b <= 1'b1 ;
	end
	else begin
		valid_b <= 1'b0  ;
	end
end
endmodule