题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
reg		[3:0] data_4d ;
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_4d <= 4'b0 ;
	end
	else if(data_valid) begin
		data_4d <= {data_4d[2:0],data} ;
	end
	else begin
		data_4d <= 4'b0 ;
	end
end
always @(*) begin
	match = (data_4d == 4'b0110) ;
end
endmodule