题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
	reg	 [2:0]	next_state;
	reg	 [2:0]	cur_state ;
	reg	 [2:0]	count ;
	parameter IDLE = 0 ,ONE =1 ,SECOND =2 ,THIRD =3,FOURTH =4 ,FITH =5,SIX =6,ERROR = 7;
	always	@(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			cur_state <= IDLE ;
		end
		else begin
			cur_state <= next_state ;
		end
	end
	always	@(*) begin
		case(cur_state) 
			IDLE : begin
				if(data == 1'b0) begin
					next_state = ONE ;
				end
				else begin
					next_state = ERROR ;
				end
			end
			ONE : begin
				if(data == 1'b1) begin
					next_state = SECOND ;
				end
				else begin
					next_state = ERROR ;
				end
			end
			SECOND : begin
				if(data == 1'b1) begin
					next_state = THIRD ;
				end
				else begin
					next_state = ERROR ;
				end
			end
			THIRD : begin
				if(data == 1'b1) begin
					next_state = FOURTH ;
				end
				else begin
					next_state = ERROR ;
				end
			end
			FOURTH : begin
				if(data == 1'b0) begin
					next_state = FITH ;
				end
				else begin
					next_state = ERROR ;
				end
			end
			FITH : begin
				if(data == 1'b0) begin
					next_state = SIX ;
				end
				else begin
					next_state = ERROR ;
				end
			end
			SIX : begin
				if(data == 1'b0) begin
					next_state = ONE ;
				end
				else begin
					next_state = ERROR ;
				end
			end
			ERROR : begin
				if(count ==3'd6 && data==0) begin
					next_state = ONE ;
				end
				else begin
					next_state = ERROR ;
				end
			end
			default :begin
				next_state = IDLE ;
			end
		endcase
	end

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n)begin
			count <=3'b0 ;
		end
		else if(count == 3'd6)begin
			count <= 3'b1 ;
		end
		else begin
			count <= count +3'b1 ;
		end
	end
	always @(*) begin
		if(!rst_n)begin
			match <=1'b0 ;
		end
		else if(count == 3'd6 && cur_state == SIX)begin
			match <= 1'b1 ;
		end
		else begin
			match <= 1'b0 ;
		end
	end 
		always @(*) begin
		if(!rst_n)begin
			not_match <=1'b0 ;
		end
		else if(count == 3'd6 && cur_state == ERROR)begin
			not_match <= 1'b1 ;
		end
		else begin
			not_match <= 1'b0 ;
		end
	end
endmodule