题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output   wire        Y   
);
    parameter s0 = 0,s1=1,s2=2,s3=3;
    reg [1:0] st,nst;
    //先写状态转移
    always @(posedge clk or negedge rst_n)begin
        if(!rst_n)
        st <= s0;
        else st <= nst;
    end

    //再写组合逻辑
    always @(*)begin
    case (st)
    s0:nst = A ? s3 : s1;
    s1:nst = A ? s0 : s2;
    s2:nst = A ? s1 : s3;
    s3:nst = A ? s2 : s0;
    endcase
    end

    //最后输出方程
   assign Y = (st ==s3 );

endmodule