题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
	reg delay_a ;
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			delay_a <=1'b0 ;
		end
		else begin
			delay_a <= a ; 
		end
	end
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			rise <=1'b0 ;
		end
		else if(a & (!delay_a))begin
			rise <= 1'b1 ;
		end
		else begin
			rise <= 1'b0 ;
		end
	end
	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			down <=1'b0 ;
		end
		else if((!a) & delay_a)begin
			down <= 1'b1 ;
		end
		else begin
			down <= 1'b0 ;
		end		
	end
endmodule