题解 | #自动贩售机2#

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
reg [2:0] count;

always @(posedge clk or negedge rst)
begin
if(!rst)
begin
count<=0;
end
else
begin
if(sel)
begin
count<= count>3'd4 ? 3'd0 :(d1 ? count+3'd1 :(d2 ? count+3'd2 : count));
end
else if(!sel)
begin
count<= count>3'd2 ? 3'd0 :(d1 ? count+3'd1 :(d2 ? count+3'd2 : count));
end
end
end
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
out1<=0;
out2<=0;
out3<=0;
end
else
begin
if(sel)
begin
out1<=0;
out2<=count>3'd4 ? 1 :0;
out3<=count>3'd4 ? count-3'd5:0;
end
else if (!sel)
begin
out1<=count>3'd2 ? 1 :0;
out2<=0;
out3<=count>3'd2 ? count-3'd3:0;
end
end
end
//*************code***********//
endmodule

`timescale 1ns/1ns
module textbench();
reg clk ,rst,d1,d2,sel;
wire  out1,out2,out3;
 seller2 u0(
	.clk(clk)  ,
    .rst(rst)  ,
	.d1(d1) ,
	.d2(d2),
	.sel(sel),
	.out1(out1),
	.out2(out2),
	.out3(out3)
);
always #5 clk=~clk;
   initial
begin
clk=1;rst=0;d1=0;d2=0;sel=0;
# 5 rst=1;
# 5 d1=1;
# 5 d1=0;
# 15 d2=1;
# 5 d2=0; 
#25 sel=1;
#10 d2=1;
#5 d2=0;
#15 d2=1; 
#5  d2=0;
#15 d2=1; 
#5  d2=0;
#20
$finish;
end

endmodule

仿真结果图如下：