题解 | #多wire连接#

`timescale 1ns/1ns

module top_module(
    a   ,
    b   ,
    x   ,
    y   ,
    z   
);

input   a   ;
input   b   ;
output  x   ;
output  y   ;
output  z   ;


assign  z = a;
assign  x = b;
assign  y = b;

endmodule