题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
wire		[7:0]		data_min_t1 ;
wire		[7:0]		data_min_t2 ;

wire		[7:0]		data_a ;
wire		[7:0]		data_b ;
wire		[7:0]		data_c ;
		

//
data_compare U_DATA_COMPARE_U1
(
	.clk(clk),
	.rst_n(rst_n),
	.data_a(a),
	.data_b(b),
	.data_min(data_min_t1)
);
data_compare U_DATA_COMPARE_U2
(
	.clk(clk),
	.rst_n(rst_n),
	.data_a(b),
	.data_b(c),
	.data_min(data_min_t2)
);
data_compare U_DATA_COMPARE_U3
(
	.clk(clk),
	.rst_n(rst_n),
	.data_a(data_min_t1),
	.data_b(data_min_t2),
	.data_min(d)
);
endmodule
module data_compare(
	input clk,
	input rst_n,
	input [7:0]data_a,
	input [7:0]data_b,

	output reg[7:0]data_min
);
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_min <= 8'b0 ;
	end
	else if(data_a >= data_b) begin
		data_min <= data_b ;
	end
	else begin
		data_min <= data_a ;
	end
end
endmodule