题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//
parameter S0=5'b00001;
parameter S1=5'b00010;
parameter S2=5'b00100;
parameter S3=5'b01000;
parameter S4=5'b10000;

reg [4:0] state,next_state;



always@(posedge clk or negedge rst)begin
	if(!rst)
		state<=S0;
	else
		state<= next_state;
end

always@(*)begin
	case(state)
			S0:		
			begin next_state=(data)? S1 : S0;
					flag=0;
			end

			S1:	
			begin
					next_state=(data)? S2 : S1;
					flag=0;
			end

			S2:		
			begin
				next_state=(data)? S3 : S2;
				flag=0;
			end

			S3:		
			begin 
				next_state=(data)? S4 : S3;
				flag=0;
			end

			S4:		
			begin
				next_state=(data)? S1 : S0;
				flag =1;
			end
		    default:
			begin
				next_state=S0;
				flag=0;
			end
		endcase
end

// always@(posedge clk or negedge rst)begin
// 	if(!rst)
// 		flag<=0;
// 	else if(state==S3)
// 		flag <=1;
// 	else
// 		flag<=0;
// end


//*************code***********//
endmodule