题解 | #序列发生器#
序列发生器
https://www.nowcoder.com/practice/1fe78a981bd640edb35b91d467341061
`timescale 1ns/1ns
module sequence_generator(
input clk,
input rst_n,
output reg data
);
reg[5 :0] q;
always@(posedge(clk) or negedge(rst_n))begin
if(!rst_n)begin
q<=6'b001011;
end
else begin
q<={q[4 :0],q[5]};
end
end
always@(posedge(clk) or negedge(rst_n))begin
if(!rst_n)begin
data<=1'b0;
end
else begin
data<=q[5];
end
end
endmodule
