题解 | #含有无关项的序列检测(和25题差不多)#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [8:0]   b;
always@(posedge clk or negedge rst_n)begin 
	if(rst_n==1'b0)
		b<=9'd0;
	else
	    b<={b[7:0],a};
end
always@(posedge clk or negedge rst_n)begin 
	if(rst_n==1'b0)
		match<=9'd0;
	else casex(b)

		9'b011XXX110: match<=9'd1;
		default:      match<=9'd0;
	    
	endcase
		

end
endmodule