题解 | #信号发生器#

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);
parameter peak=5'd20;
reg[4:0] out;
reg[3:0] cnt;
reg[1:0] pre_choice;
reg s_flag,t_flag,sflag_0;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
out=5'd0;
cnt=4'd0;
s_flag=1'b0;
t_flag=1'b0;
end
else
	if(wave_choise==2'd0)
	begin
		if(sflag_0)
		begin
         sflag_0=0;
		 s_flag=1'd0;
		 out=5'd0;
		end
	if(cnt==4'd9)
	begin
	cnt=4'd0;
	s_flag=s_flag+1;
	out=s_flag? peak :5'd0;
	end
	else
	begin
	cnt=cnt+1;
	end
	end
		else if(wave_choise==2'd1)
		begin
			begin
		out= (out==peak) ? 5'd0 : out+5'd1;  
			end
		end
			else if(wave_choise==2'd2)
			begin
					if(!t_flag)
					begin
					out=out-5'd1;
					if(out==0)
					begin
					t_flag=t_flag+1;
					end
					end
					else
					begin
					out=out+5'd1;
					if(out==peak)
					begin
					t_flag=t_flag+1;
					end
					end
			end
end

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
sflag_0=0;
end
else
begin
pre_choice<=wave_choise;
if(pre_choice!=wave_choise)
sflag_0=1;
end
end
	
					always@(*)
					begin
						wave=out;
					end
  
endmodule

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11-06 10:58
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门头沟学院 嵌入式工程师
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