题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
reg [3:0] shift_reg;

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		shift_reg <= 4'b0;
	end
	else begin
		if(data_valid)begin
			shift_reg <= {shift_reg[2:0],data};
		end
		else begin
			shift_reg <= {shift_reg[2:0],1'b0};
		end
	end
end

always @(*)begin
	if(!rst_n)begin
		match = 1'b0;
	end
	else begin
		if(shift_reg == 4'b0110)begin
			match = 1'b1;
		end
		else begin
			match = 1'b0;
		end
	end
end
endmodule