题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

	reg [8:0] seris;
 
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            begin
                match <= 1'b0;
            end
        else if ((seris[8:6] == 3'b011)&(seris[2:0] == 3'b110))
            begin
                match <= 1'b1;
            end
        else begin
            match <= 1'b0;
        end
    end
 
    always @(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
            begin  
                seris <= 1'b0;
            end
        else
            begin
                seris <= {seris[7:0],a};
            end
    end         
	

endmodule

与常规边缘检测相比修改了判断条件。