题解 | #异步复位同步释放#

//打俩拍
`timescale 1ns/1ns

module ali16(
input clk,
input rst_n,
input d,
output reg dout
 );

//*************code***********//
reg rst_n0,rst_n1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
{rst_n0,rst_n1}<=0;
else
{rst_n0,rst_n1}<={rst_n,rst_n0};
always@(posedge clk or negedge rst_n1)
if(!rst_n1)
dout<=0;
else 
dout<=d;


//*************code***********//
endmodule