题解 | #单端口RAM#
单端口RAM
https://www.nowcoder.com/practice/a1b0c13edba14a2984e7369d232d9793
`timescale 1ns/1ns
module RAM_1port(
input clk,
input rst,
input enb,
input [6:0]addr,
input [3:0]w_data,
output wire [3:0]r_data
);
// 注意使能只有一个enb,测出来是写使能，逻辑是~enb的时候是读，且是assign 连线直接读出来
reg [3:0] data_ram [127:0]; //width = 4 deep = 128
always@(posedge clk)begin
if(enb)begin
data_ram[addr] <= w_data;
end
end
assign r_data = (~rst)?4'b0:((~enb)?data_ram[addr]:4'b0);
endmodule
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