题解 | #并串转换#
并串转换
https://www.nowcoder.com/practice/296e1060c1734cf0a450ea58dd09d36c
`timescale 1ns/1ns
module huawei5(
input wire clk ,
input wire rst ,
input wire [3:0]d ,
output wire valid_in ,
output wire dout
);
//*************code***********//
reg [3:0]q;
reg [1:0]cnt;
reg rst_n;
assign dout=q[3];
assign valid_in=(cnt==0&rst_n==1)?1:0;
always@(posedge clk or negedge rst )begin
if(!rst)
rst_n<=0;
else
rst_n<=1;end
always@(posedge clk or negedge rst)
if(!rst)
cnt<=0;
else
cnt<=cnt+1;
always@(posedge clk or negedge rst)
if(!rst)
q<=d;
else if(cnt==3)
q<=d;
else
q<={q[2:0],q[3]};
//*************code***********//
endmodule
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