题解 | #可置位计数器#

//还是得看一下时序
`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
	reg [3:0]num;
	always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
		num<=0;
		else if(set)
		num<=set_num;
		else
		num<=num==4'd15?0:num+1;
	end
	always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
		zero<=0;
		else 
		zero<=num==0?1:0;
	end
	always@(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
		number<=0;
		else 
		number<=num;
	end
	


endmodule