题解 | #数据串转并电路#
数据串转并电路
https://www.nowcoder.com/practice/6134dc3c8d0741d08eb522542913583d
//这道题主要是观察时序
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg [5:0] data;
reg [2:0]cnt;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data<=0;
cnt<=0;
valid_b<=0;
end
else if(valid_a)
begin
data<={data_a,data[5:1]};
cnt<=cnt==5?0:cnt+1;
valid_b<=cnt==5?1:0;
end
else
begin
data<=data;
cnt<=cnt;
valid_b<=valid_b;
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
begin
data_b<=0;
ready_a<=0;
end
else if(cnt==5)
begin
data_b<={data_a,data[5:1]};
ready_a<=1;
end
else begin
data_b<=data_b;
ready_a<=1;
end
end
endmodule
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