题解 | #不重叠序列检测#

//打六拍 用cnt表示
//match延迟一拍确定 所以不能用前面的a_tem得用{a_tem[4:0],data}
`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
	reg [5:0]a_tem;
	reg[2:0]cnt;

	always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
	a_tem<=0;
	else 
	a_tem<={a_tem[4:0],data};
	end

	always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
	cnt<=0;
	else if(cnt==3'b101)
	cnt<=0;
	else
	cnt<=cnt+1;
	end

	always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
	match<=0;
	not_match<=0;end
	else if((cnt==3'b101)&&({a_tem[4:0],data}==6'b011100))begin
	match<=1;
	not_match<=0;end
	else if((cnt==3'b101)&&({a_tem[4:0],data}!=6'b011100))begin
	match<=0;
	not_match<=1;end
	else begin
	match<=0;
	not_match<=0;end
	end

endmodule
`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
    
    parameter ZERO=0, ONE=1, TWO=2, THREE=3, FOUR=4, FIVE=5, SIX=6, FAIL=7;
    reg [2:0] state, nstate;
    reg [2:0] cnt;
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            cnt <= 0;
        else
            cnt <= cnt==6? 1: cnt+1; 
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            state <= ZERO;
        else
            state <= nstate;
    end
    
    always@(*) begin
        if(~rst_n)
            nstate = ZERO;
        else
            case(state)
                ZERO : nstate = data? FAIL : ONE;
                ONE  : nstate = data? TWO  : FAIL;
                TWO  : nstate = data? THREE: FAIL;
                THREE: nstate = data? FOUR : FAIL;
                FOUR : nstate = data? FAIL : FIVE;
                FIVE : nstate = data? FAIL : SIX;
                SIX  : nstate = data? FAIL : ONE;
                FAIL : nstate = cnt==6&&data==0? ONE: FAIL;
                default: nstate = ZERO;
            endcase
    end
    
    always@(*) begin
        if(~rst_n) begin
            match     = 0;
            not_match = 0;
        end
        else begin
            match     = cnt==6&&state==SIX;
            not_match = cnt==6&&state==FAIL;
        end
    end
    
endmodule