题解 | #序列发生器#

对于位数不多的序列，直接蛮干，哈哈，通俗易懂！

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);

reg [2:0]cnt;
always@(posedge clk or negedge rst_n)
if(!rst_n)
	cnt <= 3'd0;
else cnt <= cnt == 3'd5 ? 0 : cnt + 1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
	data <= 0;
else if(cnt == 0 || cnt == 1 || cnt == 3)
	data <= 0;
else data <= 1;
endmodule