题解 | #自动贩售机2#

两种方案：

方案一：设计一个状态机，通过判断sel来选择下一个状态；

关于输出使用cur_stata还是next_stata。我做了个实验。两种都可以。但是使用cur_stata得用逻辑输出。next_stata是使用正常的时序输出，具体可以看下面得程序。

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
	parameter S0=0, S0_5=1, S1=2, S1_5=3, S2=4, S2_5=5, S3=6;
	reg [2:0] cur_stata, next_stata;

	always@(posedge clk or negedge rst)
		if(~rst)
			cur_stata <= S0;
		else
			cur_stata <= next_stata;

	always@(*)
		case(cur_stata)
			S0: next_stata <= d1? S0_5: d2? S1: next_stata;
			S0_5: next_stata <= d1? S1: d2? S1_5: next_stata;
			S1: next_stata <= d1? S1_5: d2? S2: next_stata;
			S1_5: next_stata <= ~sel? S0: d1? S2: d2? S2_5: next_stata;
			S2: next_stata <= ~sel? S0: d1? S2_5: d2? S3: next_stata;
			default: next_stata <= S0;
		endcase

	// always@(*)
	// 	if (~rst)
	// 		{out1, out2, out3} <= 3'b000;
	// 	else
	// 		case(cur_stata)
	// 			S1_5: {out1, out2, out3} <= ~sel? 100: 000;
	// 			S2:  {out1, out2, out3} <= ~sel? 101: 000;
	// 			S2_5:{out1, out2, out3} <= ~sel? 101: 010;
	// 			S3:{out1, out2, out3} <= ~sel? 101: 011;
	// 			default: {out1, out2, out3} <= 000;
	// 		endcase


		always@(posedge clk or negedge rst)
		if (~rst)
			{out1, out2, out3} <= 3'b000;
		else
			case(next_stata)
				S1_5: {out1, out2, out3} <= ~sel? 100: 000;
				S2:  {out1, out2, out3} <= ~sel? 101: 000;
				S2_5:{out1, out2, out3} <= ~sel? 101: 010;
				S3:{out1, out2, out3} <= ~sel? 101: 011;
				default: {out1, out2, out3} <= 000;
			endcase
//*************code***********//
endmodule

方案二：

写两个不同的状态机，根据sel来选择使用哪一个状态机。程序待完成。