题解 | #交通灯#

`timescale 1ns/1ns

module triffic_light(
		input rst_n, //异位复位信号，低电平有效
        input clk, //时钟信号
        input pass_request,
		output reg[7:0]clock,
        output wire red,
		output wire yellow,
		output wire green
    );

parameter LED_RED = 2'd0,IDLE = 2'd1,LED_GREEN = 2'd2,LED_YELLOW2GREEN = 2'd3;
reg [1:0] state,next;
//reg [7:0]clock;

always@(posedge clk or negedge rst_n)
	if(!rst_n)begin
		state <= IDLE;
	end
	else begin
		state <= next;
	end

always@(*)(1444584)
	if(!rst_n)begin
		next = IDLE;
	end
	else begin
		case(state)
			IDLE:begin
				if(clock == 8'd8)begin
					next = LED_RED;
				end
				else begin
					next = IDLE;
				end
			end
			LED_GREEN:begin
				if(clock == 8'd1)begin
					next = LED_RED;
				end
				else begin
					next = LED_GREEN;
				end
			end
			
			LED_RED:begin
				if(clock == 8'd1)begin
					next = LED_YELLOW2GREEN;
				end
				else begin
					next = LED_RED;
				end
			end
			LED_YELLOW2GREEN:begin
				if(clock == 8'd1)begin
					next = LED_GREEN;
				end
				else begin
					next = LED_YELLOW2GREEN;
				end
			end
		endcase
	end
	
always@(posedge clk or negedge rst_n)
	if(!rst_n)begin
		clock  <= 8'd10;
	end
	else begin
		case(next)
			IDLE:begin
				clock <= clock - 1'd1;
			end
			LED_GREEN:begin				
				if(pass_request)begin
					if(clock > 8'd10)begin
						clock <= 8'd10;
					end
					else begin
						clock <= clock - 1'd1;
					end
				end
				else if(clock == 8'd1)begin
					clock <= 8'd60;
				end
				else begin
					clock <= clock - 1'd1;	
				end
			end
			
			LED_RED:begin
				if((clock == 8'd1)||((state == IDLE)&&(clock <= 8'd8)))begin
					clock <= 8'd10;
				end
				else begin
					clock <= clock - 1'd1;	
				end
			end
			LED_YELLOW2GREEN:begin
				if(clock == 8'd1)begin
					clock <= 8'd5;
				end
				else begin
					clock <= clock - 1'd1;	
				end
			end
		endcase
	end

assign red = (state == LED_RED);
assign green = (state == LED_GREEN);
assign yellow = (state == LED_YELLOW2GREEN);
endmodule