题解 | #输入序列不连续的序列检测#

yeah

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

reg [2:0] state;
reg [2:0] nxt_state;
parameter zero = 0, one = 1, two = 2, three = 3, four = 4;

always @(posedge clk or negedge rst_n)
begin
	if (!rst_n)
	state <= zero;
	else 
	state <= nxt_state; 
end

always @(*)(1444584)
begin
	if (!rst_n)
	nxt_state = zero;
	else 
	case(state)
	zero: nxt_state = (data_valid & ~data)? one:zero;
	one: nxt_state = (data_valid & data)? two:one;
	two: nxt_state = (data_valid & data)? three:((data_valid & ~data)? one:two);
	three: nxt_state = (data_valid & ~data)? four:((data_valid & data)? zero:three);
	four: nxt_state = (data_valid & ~data)? one:((data_valid & data)? two:zero);
	default:nxt_state = zero;
	endcase
end

always @(*)(1444584)
begin
	if (state == four)
		match = 1;
	else 
		match = 0;
end




  
endmodule