题解 | #全加器#

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
/*
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

S-结果
C-进位
*/
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);

wire s0,c0;

add_half u_half0 (
    .A(A),
    .B(B),
    .S(s0),
    .C(c0)
);

add_half u_half1 (
    .A(s0),
    .B(Ci),
    .S(S),
    .C()
);

assign Co = (A&B) | (B&Ci) | (A&Ci) ;

endmodule