题解 | #状态机与时钟分频#

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
reg [1:0] cnt;
always@(posedge clk or negedge rst)
	if(!rst) cnt <= 2'b0;
	else if(cnt==2'b11) cnt <= 2'b0;
	else if(cnt!=2'b11) cnt <= cnt+1'b1;

always@(posedge clk or negedge rst)
	if(!rst) clk_out <= 1'b0;
	else if(cnt==2'b0) clk_out <= 1'b1;
	else clk_out<=1'b0;



//*************code***********//
endmodule