题解 | #自动贩售机2#

自动贩售机2

https://www.nowcoder.com/practice/298dec1c3dce45c881f3e53e02558828

这种方式虽然将输入打了一拍来匹配时序，作为状态机，它没有像别的答案那样（至少明面上）引入latch，但它却莫名可以跑通。不知道是不是编译器自己引入了latch呢？

这种逻辑理解虽然不如计数器简单，但输出没有使用组合逻辑来匹配testbench的时序，也算有它的独特优势。

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
    localparam S0 = 0;
    localparam S0_5 = 1;
    localparam S1 = 2;
    localparam S1_5 = 3;
    localparam S2 = 4;
//     localparam S2_5 = 4;
    
    
    reg [2:0] state, nexts;
    reg [2:0] dreg;
    
    always@(posedge clk or negedge rst)
        begin
            if(!rst)
                dreg <= 0;
            else
                dreg <= {sel,d2,d1};
        end
    
    always@(posedge clk or negedge rst)
        begin
            if(!rst)
                state <= S0;
            else
                state <= nexts;
        end
    
    always@(*)
        begin
            if(!rst)
                nexts = S0;
            else
                case(state)
                    S0: case(dreg[1:0])
                        2'b01: nexts = S0_5;
                        2'b10: nexts = S1;
                        default: nexts = state;
                    endcase
                    S0_5: case(dreg[1:0])
                        2'b01: nexts = S1;
                        2'b10: nexts = sel?S1_5:S0;
                        default: nexts = state;
                    endcase
                    S1: case(dreg[1:0])
                        2'b01: nexts = sel?S1_5:S0;
                        2'b10: nexts = sel?S2:S0;
                        default: nexts = state;
                    endcase
                    S1_5: case(dreg[1:0])
                        2'b01: nexts = sel?S2:S0;
                        2'b10: nexts = sel?S0:S0;
                        default: nexts = state;
                    endcase
                    S2: case(dreg[1:0])
                        2'b01: nexts = sel?S0:S0;
                        2'b10: nexts = sel?S0:S0;
                        default: nexts = state;
                    endcase
                    default : nexts = S0;
                endcase
        end
    
    always@(posedge clk or negedge rst)
        begin
            if(!rst)
                begin
                    out1 <= 0;
                    out2 <= 0;
                    out3 <= 0;
                end
            else if (state==S0_5)
                case(dreg)
                    3'b010: out1 <= 1;
                    default: begin out1 <= 0; out2 <= 0; out3 <= 0; end
                endcase
            else if (state==S1)
                case(dreg)
                    3'b001: out1 <= 1;
                    3'b010: begin out1 <= 1; out3 <= 1; end
                    default: begin out1 <= 0; out2 <= 0; out3 <= 0; end
                endcase
            else if (state==S1_5)
                case(dreg)
                    3'b110: out2 <= 1;
                    default: begin out1 <= 0; out2 <= 0; out3 <= 0; end
                endcase
            else if (state==S2)
                case(dreg)
                    3'b101: out2 <= 1;
                    3'b110: begin out2 <= 1; out3 <= 1; end
                    default: begin out1 <= 0; out2 <= 0; out3 <= 0; end
                endcase
            else
                begin
                    out1 <= 0;
                    out2 <= 0;
                    out3 <= 0;
                end
        end


//*************code***********//
endmodule