题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
    reg    q_temp;
    always@(posedge clk or negedge rst) begin
        if(!rst)
            q_temp <= 1'b0;
        else if(data)
            q_temp <= ~q_temp;
        else
            q_temp <= q_temp;
    end
    always@(posedge clk or negedge rst) begin
        if(!rst)
            q <= 1'b0;
        else if(q_temp)
            q <= ~q;
        else
            q <= q;
    end
//*************code***********//
endmodule