题解 | #输入序列连续的序列检测#
`timescale 1ns/1ns
module sequence_detect(
input clk,
input rst_n,
input a,
output reg match
);
parameter seq_t = 8'b0111_0001;
reg [7:0] seq_r;
always @ (posedge clk, negedge rst_n) begin
if (~rst_n) begin
seq_r <= 'b0;
end
else begin
seq_r <= {seq_r[6:0], a};
end
end
always @ (posedge clk, negedge rst_n) begin
if (~rst_n) begin
match <= 'b0;
end
else begin
match <= seq_r == seq_t;
end
end
endmodule
####笔试题思考，序列检测####
always @ (posedge clk, negedge rst) begin if(~rst) begin cnt_16 <= 0; end else begin cnt_16 <= cnt + 1; end end always @ (posedge clk, negedge rst) begin if(~rst) begin cnt_240 <= 0; end else if(flag_t_seq) begin cnt_240 <= cnt_240 + 1; end else begin cnt_240 <= 0; end end always @ (*) begin if(~rst) begin flag_t_seq <= 0; //fsync_o <= 0; end else if(tmp_seq == target_seq && cnt_240 < 239) begin flag_t_seq <= 1; end else begin flag_t_seq <= 0; end end always @ (posedge clk, negedge rst) begin if(~rst) begin cnt_3 <= 0; fsync_o <= 0; end else if(tmp_seq == target_seq) begin cnt_3 <= cnt_3 + 1; end else if (cnt_3 == 3) begin fsync_o <= 1; cnt_3 <= 0; end end endmodule
