题解 | #数据串转并电路#
数据串转并电路
http://www.nowcoder.com/practice/6134dc3c8d0741d08eb522542913583d
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg [5:0] temp;//数据寄存
reg [2:0] cnt;//计数
//valid_a与ready_a有效时，数据移位寄存
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
temp <= 6'd0;
else if(valid_a&&ready_a)
temp <= {data_a,temp[5:1]};
else
temp <= temp;
end
//设置一个6bit的计数器
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt <= 3'd0;
else if(cnt == 3'd5)
cnt <= 3'd0;
else if(~ready_a||~valid_a)
cnt <= cnt;
else
cnt <= cnt +1'b1;
end
//计数慢6次后，valid_b拉高
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
valid_b <= 1'b0;
else if(cnt == 3'd5)
valid_b <= 1'b1;
else
valid_b <= 1'b0;
end
//当计数次数到达6次时，将数据寄存进data_b中
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
data_b <= 6'd0;
else if(cnt==5&&valid_a)
data_b <= {data_a,temp[5:1]};
else
data_b <= data_b;
end
//没有复位信号时，ready_a始终拉高
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
ready_a <= 1'b0;
else
ready_a <= 1'b1;
end
endmodule
