题解 | #移位运算与乘法#

用一个状态机 需要注意rst时state也要复位

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
    reg [1:0]state;
    reg [7:0]d_temp;
    always@(posedge clk,negedge rst) begin
        if(!rst) begin
            out <= 0;
            input_grant <= 0;
            state <= 2'b00;
        end
        else begin
            case(state)
                2'b00:begin
                    d_temp <=d;
                    out <= d;
                    state <= 2'b01;
                    input_grant <= 1;
                end
                2'b01:begin
                    d_temp <=d_temp;
                    out <= d_temp + (out<<1);
                    state <= 2'b11;
                    input_grant <= 0;
                end
                2'b11:begin
                    d_temp <=d_temp;
                    out <= d_temp + (out<<1);
                    state <= 2'b10;
                    input_grant <= 0;
                end
                2'b10:begin
                    d_temp <=d_temp;
                    out <= d_temp + out;
                    state <= 2'b00;
                    input_grant <= 0;
                end
                default:begin
                    out <=0;
                    state <= 2'b00;
                    input_grant <= 0;
                end
                
            endcase
        end
    end
    

//*************code***********//
endmodule