题解 | #含有无关项的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); reg [8:0] temp_a; reg matcha,matchb; always@(posedge clk or negedge rst_n) begin if(!rst_n) temp_a <= 0; else temp_a <= {temp_a[7:0],a}; end always@(posedge clk or negedge rst_n) begin if(!rst_n) matcha <= 0; else if(temp_a[8:6] == 3'b011) matcha <= 1; else matcha <= 0; end always@(posedge clk or negedge rst_n) begin if(!rst_n) matchb <= 0; else if(temp_a[2:0] == 3'b110) matchb <= 1; else matchb <= 0; end always @(*) begin match <= matcha&&matchb; end endmodule