题解 | #自动贩售机1#

`timescale 1ns/1ns
module seller1(
    input wire clk  ,
    input wire rst  ,
    input wire d1 ,
    input wire d2 ,
    input wire d3 ,
    
    output reg out1,
    output reg [1:0]out2
);
//*************code***********//
    reg [3:0] curr_state;
    reg [3:0] next_state;
    
    always @ (posedge clk or negedge rst) begin
        if(~rst)
            curr_state<=4'b0;
        else
            curr_state<=next_state;
    end
    
    always @ (*) begin
        case (curr_state)
            4'd0:next_state<=d1?4'd1:d2?4'd2:d3?4'd3:next_state;
            4'd1:next_state<=d1?4'd2:d2?4'd4:d3?4'd5:next_state;//0.5
            4'd2:next_state<=d1?4'd4:d2?4'd3:d3?4'd6:next_state;//1
            4'd3:next_state<=4'd0;//2
            
            4'd4:next_state<=4'd0;//1.5
            4'd5:next_state<=4'd0;//2.5
            4'd6:next_state<=4'd0;//3
            default:next_state<=4'd0;
        endcase
    end
    
    always @ (*)begin
        if(~rst) begin
            out1=0;
            out2=2'b0;
        end
        else begin
            out1=(curr_state==4'd3||curr_state==4'd4||curr_state==4'd5||curr_state==4'd6);
            out2=(curr_state==4'd3)?1:(curr_state==4'd4)?0:(curr_state==4'd5)?2:(curr_state==4'd6)?3:0;                
        end
    end


//*************code***********//
endmodule