面试系列:可测性设计【3】关于测试覆盖率
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关于测试覆盖率
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随着半导体工艺的发展,可测性技术(DFT)成为每个芯片在设计中必须考虑的问题
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测试覆盖率作为DFT技术中的关键指标,受到多种因素制约
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本文针对测试覆盖率的产生算法和结果做一个分析和总结
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实际案例的具体分析和计算
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希望对大家的面试和工作有帮助
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What is DFT ?
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DFT strategies that :
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Improve quality by detectingdefects
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Make it easier to generatevectors
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Reduce vector generation time
- Reduce cost
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Why Design-for-Test?
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To increase Productivity:
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Shorter time-to-market
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Reduced design cycle
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Reduced cost
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To improve Quality:
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Reduced Defects per million(DPM)
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Improved quality of test
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What is Testability?
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Controllability:
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The ability to set a node to aspecific value
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Observability:
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The ability to observe a node’s value
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Fault Models
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Fault models:
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Stuck-at-fault
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Transition fault
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Path delay
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IDDQ
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Testable fault classes
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Detected (DT)
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det_simulation (DS)
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faults detected when the toolperforms fault simulation
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det_implication (DI)
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faults detected when the toolperforms learning analysis
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The list are only for pathdelay testing
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det_robust (DR)
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robust detected faults
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det_functional (DF)
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functionally detected faults
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Testable fault classes
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Posdet (PD):
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It includes all faults thatfault simulation identifies as possible-detected but not
hard detected
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The posdet class contains twogroups:
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posdet_testable (PT) -potentially detectable posdet faults. A higher abort
limit may reduce thenumber of these faults
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posdet_untestable (PU) - provenAU during pattern generation and hard
undetectable posdet faults
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By default, the calculationsgive 50% credit for posdet faults