题解 | #求最小公倍数#

`timescale 1ns/1ns

module lcm#(
parameter DATA_W = 8)
(
input [DATA_W-1:0] A,
input [DATA_W-1:0] B,
input             vld_in,
input            rst_n,
input             clk,
output    wire    [DATA_W*2-1:0]     lcm_out, //最小公倍数
output    wire     [DATA_W-1:0]    mcd_out, //最大公约数
output    reg                    vld_out
);

reg vld_in_d1;

always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
    begin
    
    end
    else
    begin
    
    end
end

reg [3:0] compare_state;
parameter STATE_IDLE = 4'b0001,
          STATE_COMPARE = 4'b0011;
reg [DATA_W-1:0] data1,data2;
reg [DATA_W-1:0] mcd;
reg [DATA_W*2-1:0] mult;

always@(posedge clk or negedge rst_n)
begin
    if(!rst_n)
    begin
        data1<='d0;
        data2<='d0;
        mcd<='d0;
        vld_out<='d0;
        mult<='d0;
        compare_state<=STATE_IDLE;
    end
    else
    begin
        case(compare_state)
            STATE_IDLE:
            begin
                if(vld_in)
                begin
                    data1<=A;
                    data2<=B;
                    mult<=A*B;
                    compare_state<=STATE_COMPARE;
                end
                else
                begin
                    data1<='d0;
                    data2<='d0;
                    mcd<='d0;
                    vld_out<='d0;
                    mult<='d0;
                end
            end
            
            STATE_COMPARE:
            begin
                if(data1==data2)
                begin
                    vld_out<='d1;
                    mcd<=data1;
                    compare_state<=STATE_IDLE;
                end
                else
                begin
                    if(data1>data2)
                    begin
                        data1<=data1-data2;
                        data2<=data2;
                    end
                    else if(data1<data2)
                    begin
                        data1<=data1;
                        data2<=data2-data1;
                    end
                end
            end
            
            default: compare_state<=STATE_IDLE;
        endcase
    end
end

assign mcd_out = mcd;
assign lcm_out = mult/mcd;







endmodule