verilog求解hdlbits中rule100

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output reg[511:0] q ); 
	
    int i;
    always @(posedge clk ) begin
        if(load)
            q <= data;
        else begin
            q <= ~(data >> 1) & data | data << 1 ^ data;
            
            
            
        end
    end
endmodule

这个为什么不能这样写？