【开卷】第35期 AMD超威半导体数字芯片B（设计验证后端）

A. T1

B. T2

C. T3

D. T1+T2

2. What's the main usage of Scan shift registers? ()

A. Provide Control & Observe capability

B. Provide Lock and un-lock statement

C. Provide Control & stability check

D. Provide clock observation

3. Which stage of detecting a fault is at least cost to a company? (  )

A. Wafer

B. Packaged chip

C. Board

D. System

4. Which of the following expressions is true?

A. a=4'df

B. C=3 'd8

C. B=5 'h1

D. d=3 'b2

5. Which of the followings is not allowed to be in an interface class?(  )

A. Pure virtual methods

B. Type declarations

C. Cover groups

D. Parameter declarations

6. Which of the following arrays need new constructor in system Verilog?

A. Multidimensional arrays

B. Dynamic arrays

C. Associative arrays

D. Queues.

7. Which one of the following items can be considered to decrease the power of a design? (  )

A. use high Vt cells

B. increase clock frequency.

C. add clock gating

D. decrease voltage supply.

8. Which descriptions are correct for System-Verilog language?(  )

A. Inheritance

B. Classed based OOP

C. Prototype -based OOP

D. Polymorphism

D. Encapsulation

9. Memory BIST can test below elements in the design. (  )

A. Address decoder

B. Memory Array

C. ECC(Error Check & Correct) logic

D. Memory access control logic

10. Select the items which could contribute to functional coverage? (  )

A. SV Cover groups

B. SV Assert Property

C. PSL

D. SV Cover Property

11. Which are the main components of a testbench? (  )

A. Monitor

B. Checker

C. Scoreboard

D. Reference model

E. FIFO

12. The time required for an input data to settle________ the triggering edge of clock is known as “Setup Time”. (  )

A. Before

B. During

C. After

D. All of the above

13. Which equation compute the local skew in below circuit? (  )

A. Path1-Path2

B. Path3-Path2

C. Path3-Path1

D. Path4-Path2

14. Which of the following is having highest priority at final stage (post routed) of the design?

A. Setup violation

B. Hold violation

C. Skew

D. None

15. Which of the following tools can be used for timing tape out sign-off? (  )

A. Modelsim

B. Primetime

C. Redhawk

D. Design compiler

16. We need to define clock specifications in SDC file, using commands like below:

Create_clock -name GFXCLK -period 600 -waveform {0 300 }

what can we know from this command? (  )

A. Clock frequency

B. Clock duty cycle

C. Clock source latency

D. Clock name

17. Which ways are efficient for cross talk fix?(  )

A. Use wide net

B. upsize driving cell

C. add keep out margin

D. downsize driving cell

18. How to fix the EM problem on signal net?

A. set non default rule for violation signal net, increase wire width

B. set non default rule for violation signal net, decrease wire width

C. decrease the signal net fanout

D. increase the signal net output load

19. Which solutions can be used to reduce parasitic for critical net? (  )

A. Reducing Interconnect Resistance

B. Increasing Wire Spacing

C. Reducing parasitic for Correlated Nets

D. Routing in lower (thinner) metals

20.下列不属于嵌入式设计处理器本身带有的基本接口是(   )

A.串口

B. PCIE

C.并口

D.AD/DA

21. 已知下左国中施密特触发器为右图中所示电路，电源电压是10V, R1-10KΩ，R2=20KΩ，该多谐振荡器中的电路参数VDD=10V，R=10kΩ，C=0.01uF，则该电路的振荡周期是（  ）

A. 0.2197ms

B. 0.4297ms

C. 0.1099ms

D. 0.3296ms

22. In Linux system, which of following commands can be used to mount a U-disk to the system（）

A. mount /dev/hda /mnt/udisk

B. mount /dev/sdb1 /mnt/udisk

C. mount /dev/fd0 /mnt/udisk

D. umount -n /mnt/udisk

23.请判断以下哪些电路是时序逻辑电路（）

A.计数器

B.寄存器

C.译码器

D.触发器

24.如图所示，若驱动门A的输出电压高低电平的定义为VAOHmin=2.4V, VAOLmax=0.4V,那么它连接到的接收门B的输入电压需要定义的高低电平可能为:

A. VBIHmin=2.8V

B. VBIHmin=2.0V

C. VBILmax=0.8V

D. VBILmax=0.2V

25. 为了避免50Hz电网电压的干扰进入放大器，应选用哪种滤波器?

A.带通

B.带阻

C.低通

D.高通

26. In amplification mode, which of the following is correct for this transistor?（）

A. VC>VB>VE

B.VC<VB<VE

C.VB<VC<VE

D. VB>VC>VE

27. The following figure shows the CMOS inverter circuit, which is composed of two enhanced MOSFET, one N-channel structure, the other is P-channel structure. Which of the following conditions is necessary to make the circuit function?（）

A. VDD= (VTN-|VTP|)

B. VDD> (VTN+|VTP|)

C. VDD < VTN+|VTP|)

D. VDD= (VTN+|VTP|)

28. Which of the following descriptions is true of digital signals（）

A. It is a discrete signal in time, but it cannot be a discrete signal numerically

B. The signal is discontinuous in time and always occurs in a sequence of discrete moments

C. Numerically quantized, can only be evaluated by a finite number of increments or steps

D. It is a continuous signal in time, and it must be a discrete signal numerically

29. The main performance indexes of computer network are? (  )

A. rate

B. bandwidth

C. handling capacity

D. delay

E. use ratio