题解 | #时钟分频（偶数）#

````timescale 1ns/1ns
//注意clk_out4的翻转
module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
    reg[1:0]cnt;
    reg     clk_out2_tmp;
    reg     clk_out4_tmp;
    reg     clk_out8_tmp;
    always @(posedge clk_in or negedge rst)begin
        if(~rst)
            cnt <= 0;
        else  
            cnt <= cnt + 1'b1;
    end
    
    always @(posedge clk_in or negedge rst)begin
        if(~rst)
            clk_out2_tmp <= 0;
        else
            clk_out2_tmp <= ~clk_out2_tmp;
    end
    
    always @(posedge clk_in or negedge rst)begin
        if(~rst)begin
            clk_out4_tmp <= 0;
            clk_out8_tmp <= 0;
        end else begin
            if(cnt == 2'd0)begin
                clk_out4_tmp <= ~clk_out4_tmp;
                clk_out8_tmp <= ~clk_out8_tmp;
            end else if(cnt == 2'd2)
                clk_out4_tmp <= ~clk_out4_tmp;
        end
    end
    
    assign clk_out2 = clk_out2_tmp;
    assign clk_out4 = clk_out4_tmp;
    assign clk_out8 = clk_out8_tmp;
//*************code***********//
endmodule