题解 | #状态机-重叠序列检测#

````timescale 1ns/1ns
//本题注意一个细节，要求输出寄存一拍，所以输出状态用curr_state（很关键）
//用next_state下一拍出结果
module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
localparam IDLE = 0,
            S1  = 1,
            S2  = 2,
            S3  = 3,
            S4  = 4;    
    reg[2:0]curr_state,next_state;
    
    always @(posedge clk or negedge rst)
        if(~rst)
            curr_state <= IDLE;
        else
            curr_state <= next_state;
    
    always @(*)begin
        case(curr_state)
            IDLE: next_state = (data==1'b1)? S1: IDLE;
            S1  : next_state = (data==1'b0)? S2: S1; 
            S2  : next_state = (data==1'b1)? S3: IDLE;
            S3  : next_state = (data==1'b1)? S4: S2;
            S4  : next_state = (data==1'b1)? S1: S2;
            default: next_state = IDLE;
        endcase
    end
    
    always @(posedge clk or negedge rst)begin
        if(~rst)
            flag <= 0;
        else if(curr_state == S4)
            flag <= 1'b1;
        else
            flag <= 1'b0;
    end

//*************code***********//
endmodule