题解 | #整数倍数据位宽转换8to16#

````timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);
    reg flag;
    reg[15:0] data_cache;
    always @(posedge clk or negedge rst_n)begin
        if(~rst_n)
            flag <= 0;
        else if(valid_in)
            flag <= ~flag;
    end
    
    always @(posedge clk or negedge rst_n)begin
        if(~rst_n)
            data_cache <= 0;
        else if(valid_in)
            data_cache <= {data_cache[7:0],data_in};
    end
    
    always @(posedge clk or negedge rst_n)begin
        if(~rst_n)begin
           valid_out <= 0;
            data_out <= 0;
        end else if(flag && valid_in)begin
            data_out <= {data_cache[7:0],data_in};
            valid_out <= 1'b1;
        end else 
            valid_out <= 0;
    end

endmodule