题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12( input clk ,
input rst_n , input valid_in , input [7:0] data_in ,

output  reg			   valid_out,
output  reg [11:0]   data_out

);

reg[1:0]cnt;
reg[11:0]data_cache;

always @(posedge clk or negedge rst_n)begin
    if(~rst_n)
        cnt <= 0;
    else if(valid_in && cnt == 2)
        cnt <= 0;
    else if(valid_in)
        cnt <= cnt + 1'b1;
end

always @(posedge clk or negedge rst_n)begin
    if(~rst_n)
        data_cache <= 0;
    else if(valid_in)
        data_cache <= {data_cache[3:0],data_in};
end

always @(posedge clk or negedge rst_n)begin
    if(~rst_n)begin
        valid_out <= 0;
        data_out <= 0;
    end else if(valid_in && cnt == 2'd1)begin
       valid_out <= 1'b1;
        data_out <= {data_cache[7:0],data_in[7:4]};
    end else if(valid_in && cnt == 2'd2)begin
       valid_out <= 1'b1;
        data_out <= {data_cache[3:0],data_in};
    end else begin
       valid_out <= 0; 
    end
end

endmodule