题解 | #不重叠序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, output reg match, output reg not_match );

//解法一 /*若array_out=1,说明array里的数据完全换成 新数据，此时新来的数据必须放在低位 该法把移位寄存器当成了计数器，比较新颖 */

   reg[5:0]array;
   reg     array_out;
   always @(posedge clk or negedge rst_n)
        if(~rst_n)begin
            array <= 6'd1;
            array_out <= 1'b0;
        end else if(~array_out)begin
            array <= {array[4:0],data};
            array_out <= array[5];//同一拍
        end else begin
            array <= {5'd1,data};
            array_out <= 0;
        end
        //条件为同一拍数据
    //assign    match        =    (array_out && array==6'b011_100) ? 1 : 0;
    //assign    not_match    =    (array_out && ~(array==6'b011_100)) ? 1 :0;

/*//方法二 计数器
reg[2:0]cnt;
reg[5:0]data_tmp;
always @(posedge clk or negedge rst_n)
    if(~rst_n)begin
        cnt <= 0;
        data_tmp <= 0;
    end else if(cnt == 3'd5)begin
        cnt <= 0;
        data_tmp <= {data_tmp[4:0],data};
    end else begin
        cnt <= cnt + 1'b1;
        data_tmp <= {data_tmp[4:0],data};
    end
always @(posedge clk or negedge rst_n)
    if(~rst_n)begin
        match <= 0;
        not_match <= 0;
    end else if(cnt == 3'd5 && {data_tmp[4:0],data} == 6'b011100)begin
        match <= 1'b1;
        not_match <= 1'b0;
    end else if(cnt == 3'd5 && {data_tmp[4:0],data} != 6'b011100)begin
        match <= 1'b0;
        not_match <= 1'b1;
    end else begin
        not_match <= 1'b0;
        match <= 1'b0;
    end*/


/*//方法三（改正了某位同学的条件）
reg[2:0]cnt;
reg     rom_cache;
reg     det_rom_che;
always @(posedge clk or negedge rst_n)
    if(~rst_n)
        cnt <= 0;
    else 
        cnt <= (cnt == 3'd5)? 0 : cnt+1;

always @(*)begin
        case(cnt)
            0: rom_cache = 0;
            1: rom_cache = 1;
            2: rom_cache = 1;
            3: rom_cache = 1;
            4: rom_cache = 0;
            5: rom_cache = 0;
            default: rom_cache = 0;
        endcase
end
always @(posedge clk or negedge rst_n)begin
    if(~rst_n)
        det_rom_che <= 1;
    else if(cnt == 3'd5)
        det_rom_che <= 1'b1;
    else 
        det_rom_che <= det_rom_che && (~(rom_cache^data));
end

always @(posedge clk or negedge rst_n)begin
    if(~rst_n)begin
        match <= 0;
    end else if((det_rom_che && (~(rom_cache^data))) && cnt == 3'd5)begin
        match <= 1'b1;
    end else begin
        match <= 1'b0;
    end
end
always @(posedge clk or negedge rst_n)begin
    if(~rst_n)begin
        not_match <= 0;
    end else if(~(det_rom_che && (~(rom_cache^data))) && cnt == 3'd5)begin
        not_match <= 1'b1;
    end else begin
        not_match <= 1'b0;
    end
end */
parameter   IDLE = 0,
            S1 = 1,
            S2 = 2,
            S3 = 3,
            S4 = 4,
            S5 = 5,
            S6 = 6,
            NOT_MATCH = 7;
reg[2:0]cnt;
reg[2:0]curr_state,next_state;

always @(posedge clk or negedge rst_n)
    if(~rst_n)
        cnt <= 0;
    else
        cnt <= (cnt==3'd5)? 0:cnt + 1'b1;

always @(posedge clk or negedge rst_n)begin
    if(~rst_n)
        curr_state <= IDLE;
    else
        curr_state <= next_state;
end    
    always @(*)begin
        case(curr_state)
            IDLE: next_state = (data==1'b0)? S1:NOT_MATCH;
            S1  : next_state = (data==1'b1)? S2:NOT_MATCH;
            S2  : next_state = (data==1'b1)? S3:NOT_MATCH;
            S3  : next_state = (data==1'b1)? S4:NOT_MATCH;
            S4  : next_state = (data==1'b0)? S5:NOT_MATCH; 
            S5  : next_state = (data==1'b0)? IDLE:NOT_MATCH;
            //S6  : next_state = (data==1'b0)? S1:NOT_MATCH;
            NOT_MATCH:next_state = (cnt==3'd5)? IDLE:NOT_MATCH;
            default:next_state = IDLE;
        endcase
    end
                
    always @(posedge clk or negedge rst_n)begin
        if(~rst_n)begin
            match <= 1'b0;
            not_match <= 1'b0;
        end else if(cnt==3'd5 && curr_state==S5 && data==1'b0)begin
            match <= 1'b1;
            not_match <= 1'b0;
        end else if(cnt==3'd5 )begin
            match <= 1'b0;
            not_match <= 1'b1;               
        end else begin
            match <= 1'b0;
            not_match <= 1'b0;                   
        end
    end  

endmodule