题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
    input clk,
    input rst_n,
    input a,
    output reg match
    );
    
    /*reg [7:0]a_tmp;
    always @(posedge clk or negedge rst_n)
        if(~rst_n)
            match <= 1'b0;
        else if(a_tmp == 8'b01110001)
            match <= 1'b1;
        else
            match <= 1'b0;
    
    always @(posedge clk or negedge rst_n)begin
        if(~rst_n)
            a_tmp <= 8'd0;
        else 
           // a_tmp <= {a,a_tmp[7:1]};
            a_tmp <= {a_tmp[6:0],a};
    end*/
    localparam IDLE =0,ONE =1,TWO =2,THREE =3,FOUR =4,
             FIVE =5,SIX =6,SEVEN =7,EIGHT =8;
    reg[3:0]curr_state,next_state;
    
    always @(posedge clk or negedge rst_n)
        if(~rst_n)
            curr_state <= IDLE;
        else
            curr_state <= next_state;
    
    always @(*)begin
        case(curr_state)
            IDLE:   next_state =(a==0)?ONE:IDLE;
            ONE:    next_state =(a==0)?ONE:TWO;
            TWO:    next_state =(a==0)?ONE:THREE;
            THREE:  next_state =(a==0)?ONE:FOUR;
            FOUR:   next_state =(a==0)?FIVE:IDLE;
            FIVE:   next_state =(a==0)?SIX:TWO;
            SIX:    next_state =(a==0)?SEVEN:TWO;
            SEVEN:  next_state =(a==0)?ONE:EIGHT;
            EIGHT:  next_state =(a==0)?ONE:THREE;
            default:next_state =IDLE;
        endcase      
    end
    always @(posedge clk or negedge rst_n)
        if(~rst_n)
            match <= 1'b0;
    else if(curr_state == EIGHT)
            match <= 1'b1;
        else
            match <= 1'b0;
        
        
endmodule