题解 | #简易秒表#

两段过程块分别处理秒和分。

完整代码

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
	);
    
    always@(negedge rst_n or posedge clk)begin
        if(~rst_n)
            second <= 0;
        else if(minute==60)
            second <= 0;
        else
            second <= second==60? 1: second+1;
    end
    
    always@(negedge rst_n or posedge clk)begin
        if(~rst_n)
            minute <= 0;
        else minute <= second==60? minute+1: minute;
    end
    
	
	
endmodule