题解 | #状态机-非重叠的序列检测#

采用标准的三段式风格编写状态机FSM，由于含有初始状态IDLE，故一般需定义的状态数等于序列数+1。非重叠检测下，当输出flag=1时，令当前状态CS=IDLE，避免重复检测。

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//

    parameter IDLE=0, A=1, B=2, C=3, D=4, E=5;
    reg[2:0]CS,NS;
    always@(negedge rst or posedge clk)begin
        if(~rst)
            CS <= 0;
        else
            CS <= NS;
    end
    always@(*)begin
        if(~rst)
            flag = 0;
        else if(CS == E)
            flag = 1;
        else
            flag = 0;
    end
    always@(*)begin
        if(flag)
            NS = IDLE;
        else
            case(CS)
                IDLE:if(data) NS = A; else NS = IDLE;
                A:if(~data) NS = B; else NS = A;
                B:if(data) NS = C; else NS = IDLE;
                C:if(data) NS = D; else NS = B;
                D:if(data) NS = E; else NS = B;
                E:if(data) NS = A; else NS = B;
            endcase
    end

//*************code***********//
endmodule