题解 | #加减计数器#

同样也不难，但根据波形要求，要添加一个中间计数器num。

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input mode,
	output reg [3:0]number,
	output reg zero
	);
    reg[3:0] num;
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            num <= 0;
        else if(mode)
            num <= num==9? 0: num+1;
        else
            num <= num==0? 9: num-1;
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            number <= 0;
        else
            number <= num;
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            zero <= 0;
        else
            zero <= num==0;
    end
endmodule