题解 | #非整数倍数据位宽转换24to128#
非整数倍数据位宽转换24to128
http://www.nowcoder.com/practice/6312169e30a645bba5d832c7313c64cc
简析
输入:valid_in, data_in[23:0]
输出:valid_out,data_out[127:0]
输入数据是24bit,输出数据是128bit。因为,所以每输入16个有效数据,就可以产生三个完整的输出。因此设置一个仅在输入数据有效时工作的计数器cnt
,计数范围是0-15。
reg [3:0] cnt;
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
cnt <= 0;
else
cnt <= ~valid_in? cnt:
cnt==15 ? 0 :
cnt+1;
end
然后设置一个数据暂存器data_lock
,每当输入有效时,将数据从低位移入。
reg [127:0] data_lock;
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
data_lock <= 0;
else
data_lock <= valid_in? {data_lock[103:0], data_in}: data_lock;
end
由上图易得,每当计数器cnt
计数到5、10、15时,data_out
要进行更新,并拉高valid_out
一个周期。
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
valid_out <= 0;
else
valid_out <= (cnt==5 || cnt==10 || cnt==15)&&valid_in;
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
data_out <= 0;
else if(cnt==5)
data_out <= valid_in? {data_lock[119:0], data_in[23:16]}: data_out;
else if(cnt==10)
data_out <= valid_in? {data_lock[111:0], data_in[23: 8]}: data_out;
else if(cnt==15)
data_out <= valid_in? {data_lock[103:0], data_in[23: 0]}: data_out;
else
data_out <= data_out;
end
代码
`timescale 1ns/1ns
module width_24to128(
input clk ,
input rst_n ,
input valid_in ,
input [23:0] data_in ,
output reg valid_out ,
output reg [127:0] data_out
);
reg [3:0] cnt;
reg [127:0] data_lock;
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
cnt <= 0;
else
cnt <= ~valid_in? cnt:cnt+1;
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
valid_out <= 0;
else
valid_out <= (cnt==5 || cnt==10 || cnt==15)&&valid_in;
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
data_lock <= 0;
else
data_lock <= valid_in? {data_lock[103:0], data_in}: data_lock;
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
data_out <= 0;
else if(cnt==5)
data_out <= valid_in? {data_lock[119:0], data_in[23:16]}: data_out;
else if(cnt==10)
data_out <= valid_in? {data_lock[111:0], data_in[23: 8]}: data_out;
else if(cnt==15)
data_out <= valid_in? {data_lock[103:0], data_in[23: 0]}: data_out;
else
data_out <= data_out;
end
endmodule
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