题解 | #不重叠序列检测#设置了一个带初始化的waiting状态

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, output reg match, output reg not_match ); parameter idle=3'b000; parameter state1=3'b001; parameter state2=3'b010; parameter state3=3'b011; parameter state4=3'b100; parameter state5=3'b101; parameter waiting=3'b110;

reg [2:0] state;
reg [2:0] count;

always @ (posedge clk or negedge rst_n)begin
    if(~rst_n)begin
        state<=idle;match<=0;not_match<=0;count<=0;
    end
    else begin
        case(state)
            idle:begin
                match<=0;
                not_match<=0;
                if(data==0)begin
                    state<=state1;
                end
                else begin
                    state<=waiting;
                    count<=5;
                end
            end
            
            state1:begin
                if(data==1)begin
                    state<=state2;
                end
                else begin
                    state<=waiting;
                    count<=4;
                end
            end
            
            state2:begin
                if(data==1)begin
                    state<=state3;
                end
                else begin
                    state<=waiting;
                    count<=3;
                end
            end
            
            state3:begin
                if(data==1)begin
                    state<=state4;
                end
                else begin
                    state<=waiting;
                    count<=2;
                end
            end
            
           state4:begin
               if(data==0)begin
                    state<=state5;
               end
               else begin
                    state<=waiting;
                    count<=1;
                end
            end
            
            state5:begin
               if(data==0)begin
                    match<=1;
                    not_match<=0;
               end
               else begin
                    match<=0;
                    not_match<=1;
               end
               state<=idle;
            end
            
            waiting:begin
                count<=count-1;
                if(count==1)begin
                    state<=idle;
                    not_match<=1;
                    match<=0;
                end
                else begin
                    state<=waiting;
                end
            end
            
        endcase
    end
end

endmodule