题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit( input C , input clk , input rst_n, output wire Y
); reg [1:0] cur_state; reg [1:0] nex_state; reg y1;

assign Y=y1;

always @(posedge clk or negedge rst_n)begin
    if(~rst_n)begin
        cur_state<=0;
    end
    else begin
        cur_state<=nex_state;
    end
end

always @(*)begin
    y1=cur_state[1]&(cur_state[0]|C);
end

always @(*)begin
    nex_state[1]=cur_state[1]&(cur_state[0]|C) | ~cur_state[1]&cur_state[0]&~C;
    nex_state[0]=~cur_state[1]&cur_state[0] | cur_state[0]&~C | ~cur_state[1]&C; 
end

endmodule